Chipsculpt is your partner for complete verification solutions from concept to silicon.
Chipsculpt verification experts enable you to ramp up quickly on verification using the latest industry methodologies at chip level and block level. Our methodology helps shorten verification cycles for complex SoCs at all stages of development.
Coverage driven Verification
Assertion based Verification
Full Chip Verification
Coverage driven verification
CDV is an integral part of our verification methodology. This helps in creating a very robust verification infrastructure with an optimal use of tools and engineering resources. Chipsculpt has embraced this methodology for all its verification services and advocates use by its clients.
Service will involve
Develop verification strategy based on industry standard methodologies like VMM, RVM, AVM, OVM and open source Teal and Truss.
Multi-disciplinary test plan development based on inputs from design, SW and system team.
Implement random generation testbenches with configurable and reusable drivers, monitors and self-checks.
Implement functional coverage model based on the testplan
Introduce blocks into company regression platform.
Block/chip sign-off based on functional coverage analysis and code coverage convergence.
We work to ensure first time right silicon
Assertion based verification
White box assertion development for design IPs.
Experience in development of Assertion IPs for standard interfaces i.e. AHB, PCI, PCI Express, USB.
Develop assertions using SVA, PSL and OVA.
Companies need to adopt newer tools and verification methodologies to benefit from increased effectiveness and hence increase their design robustness.
Chipscult provides services to enable quick migration of legacy designs and VIP into the new infrastructure.
Chipsculpts expertise lies in migration of verification environment from
Verilog/VHDL to SystemVerilog/Vera/C++/e
Vera to SystemVerilog/e/C++
e to SV/C++/Vera
C++ to SV/Vera/e.
Mixed language VHDL/Verilog into Verilog.
Chipsulpt helps with development of VIP that is tool and methodology independent. Chipsculpts guidelines for VIP development take into consideration ease of use, efficient run times and reusability over multiple projects.
VIPs can be in the form of models using RVM, OVM, VMM or even assertions using SVA.
Hardware Software co-verification
Chipsculpt realizes that emulation has become more and more of a choice for verification before silicon as the chips have become more complex and more dependent on SW.
Running SW on the emulation board identifies a bugs on the HW-SW boundary. These bugs are critical and better be resolved before hand.
Chipsculpt provides services for regression strategies on emulation and also simulating using tools like Seamless for identifying problems on the emulator.
Chipsculpt provides formal verification services for various stages of design development cycle.
RTL-Gates (rtl - synthesized gates)
Gates-Gates (synthesis vs post dft, post dft vs post layout etc.)
Full chip verification
Comprehensive verification infrastructure environment for full chip verification platform. Test plans for unit level, chip level, boundary conditions, etc.
Languages: System Verilog, C++, Vera, e, Verilog, VHDL, Perl.
Tools: Modelsim, VCS, Seamless
Methodologies: RVM, AVM, VMM, OVM, Teal and Truss
DFT Strategy and methodology setup for Internal Scan, Boundary Scan, Memory BIST etc.
Executing for Test Synthesis, ATPG and test vector generation
JTAG, BSDL and WGL file generation, DFT rule checking and debugging, scan simulations
Customize Tap Controller (JTAG) to run BIST and Scan via custom instructions
Our team is experienced in designing 10+ million gates designs from concept to parts. We have extensive experience in integrating a variety of IP (MAC, Serdes, Processor Cores etc.), designs with multiple clock domains etc. We have also done numerous FPGA designs, and FPGA to ASIC conversions. Our robust design guidelines and methodology ensures first pass silicon success for our customers.
Specification Generation, Architecture and Design Partitioning
IP design, turnkey projects, block designs
RTL Design (System Verilog, Verilog, VHDL)
Synthesis (multi vt libs, clock gating)
Chipsculpt members have taped out multiple designs targeted to various processes from 0.13u to 60nm for foundries such as TSMC, IBM, Philips etc. We are experienced in high speed IO and designs, SERDES, low power and mixed signal designs and timing closure techniques.
Our physical design services can be used for rtl to gdsII or netlist to gdsII flows.
Synthesis RTL to Gates
Test Insertion - SCAN, BIST, JTAG
Design Planning and Silicon Virtual Prototyping
Automatic Place and Route
Signal and Power Analysis
Static Timing Analysis with extracted delays
Physical Verification (DRC, LVS, ERC)
GDS II release
Chipsculpt helps its clients to prototype their ASIC designs on FPGAs to develop an emulation platform.
Design Partition of ASIC on multiple FPGAs
Implementation and testing of firmware on emulator platform with the help clients SW team.
Conversion of FPGA to structured ASICs, ASICs
FPGA Solutions development
Chipsculpt provides support services for FPGA solutions. We get involved with the client at early stages of the design architecting. We provide inputs on design based on the domain based on our experience working with other client.
Take ownership of sub-blocks and deliver a working solution with firmware running with it.
Develop IP cores for reuse on various projects
Develop HW accelerators to improve performances of the design on FPGAs
Chipsculpt takes up the responsibility to re-architect sub-blocks and top architecture of existing design and re-engineer it for high speed or high integration using the latest tools and methodologies from the FPGA vendors.